Field of the Invention
This invention relates generally to comparator circuits, and more particularly to comparator circuits used in column-parallel single-slope analog-to-digital converters (ADCs).
Description of the Related Art
Image sensors generally include an array of pixels arranged in rows and columns. One common approach to reading out the voltages produced by the pixels in each column is to use column-parallel single-slope ADCs. A typical arrangement is shown in FIG. 1. A voltage from each column, Vin0, Vin1, . . . , Vinx is provided to one input of respective comparators A0, A1, . . . , Ax, each of which also receives a shared (or ‘global’) voltage ramp Vramp produced by a ramp generator 10. During each row readout period, Vramp increases linearly and covers the full input signal range. The output of each comparator toggles when Vramp exceeds its column voltage (Vin0, Vin1, . . . , Vinx). The system typically includes a common counter 12, and the columns typically include respective memory locations 14, 16, 18; when the output of each column's comparator toggles, the current counter value is stored in the column's memory location and is a digital representation of the column voltage. Note that a comparator and a memory location are located in each column.
As noted above, each comparator receives a common ramp voltage Vramp, which is generated by a ramp generator such as the basic ramp generator 10 shown in FIG. 2. A capacitor Cramp is connected to a constant current source 20 via a switch 22 operated with an enable signal ‘en’, and to a constant potential such as ground via a switch 24 operated with a reset signal ‘rst’. In operation, closing switch 22 causes Vramp to start increasing linearly, and closing switch 24 causes Vramp to reset to the constant potential such as ground.
Several types of comparator circuits are used in column-parallel single-slope ADCs. An example of an “AC-coupled” comparator circuit is shown in FIG. 3a, and a timing diagram which illustrates the operation of the circuit is shown in FIG. 3b. The column voltage (Vin) is connected to one side of a switch 40 operated with a control signal p1d; a sampling capacitor Cs is connected between the other side of the switch and one of the inputs of comparator A0. A reset capacitor Crst is connected to the other comparator input, which is initialized to a voltage Vrst via switches 42 and 44, each of which is operated with a control signal p1. Global voltage ramp Vramp is connected to the input side of Cs via a switch 46 operated with a control signal p2.
As shown in FIG. 3b, during the sampling phase (signals p1 and p1d are high and p2 is low) switches 40, 42 and 44 are closed such that Vrst is stored on Crst, and Vin−Vrst is stored on Cs. During the ramping phase (signals p1 and p1d are low and p2 is high), switch 46 is closed, thereby applying Vramp to the input side of Cs. As Vramp increases, at some point it exceeds Vin. Because of charge conservation, at this instant the voltage at node Vx exceeds Vrst and the output q of A0 toggles.
AC-coupling the input signal and the ramp voltage as illustrated in FIG. 3a enables the comparator operating point and propagation delay to be constant regardless of the input voltage Vin. However, the AC-coupled comparator circuit of FIG. 3a still suffers from several inherent problems. Global voltage ramp Vramp is affected by both comparator kickback and a varying capacitive load, the latter resulting from variation in the operating point of the comparator input devices as the comparator nears and crosses the tripping point. Both effects may degrade the quality of the global voltage ramp Vramp and consequently lead to ADC non-linearity and crosstalk among ADCs. Another drawback is that the permissible input swing for input voltage Vin is limited to approximately Vdd/2, where Vdd is the circuit's supply voltage. This is explained as follows:
With reference to FIG. 3a, the node voltage at the junction of Cs and the comparator is Vx. As shown in FIG. 3b, Vx(t) is plotted for minimum and maximum value of Vin with a solid and a dotted line, respectively. The minimum value of Vx is reached at the beginning of the ramp and is given by:Vx,min=Vrst−Vin,max+Vramp,min,The maximum value of Vx is reached at the end of the ramp and is given by:Vx,max=Vrst−Vin,min−Vramp,max.Here Vin,min and Vin,max define the smallest and largest possible values of Vin, and Vramp,min and Vramp,max define the smallest and largest ramp voltages.Therefore:Vx,max−Vx,min=(Vramp,max−Vramp,min)+(Vin,max−Vin,min)If Vin,max=Vramp,max and Vin,min=Vramp,min (i.e., the ramp spans the entire input range of the comparator), then Vx,max−Vx,min=2(Vin,max−Vin,min).If during the ramping phase Vx should exceed one of the supply rails, switch 42 or switch 44 would leak and capacitor Cs would no longer be floating. This would dramatically increase the load on the shared voltage ramp and corrupt it. To prevent this strong crosstalk scenario, one must ensure that Vx,max−Vx,min≈Vdd. It follows that Vin,max−Vin,min≈Vdd/2.